The transfer of new information into a register is referred to... | Agrigyan

• Base-4 (Quaternary) Arithmetic Addition:
• Given $m = (313)_4$ and $n = (322)_4$:
• Perform column-by-column addition from right to left using base 4 rules:
• Least significant digit ($4^0$):

$$3 + 2 = 5_{10} = (1 \times 4) + 1 \implies \text{Digit } 1, \quad \text{Carry } 1$$

• Middle digit ($4^1$):

$$1 + 2 + (\text{carry } 1) = 4_{10} = (1 \times 4) + 0 \implies \text{Digit } 0, \quad \text{Carry } 1$$

• Most significant digit ($4^2$):

$$3 + 3 + (\text{carry } 1) = 7_{10} = (1 \times 4) + 3 \implies \text{Digit } 3, \quad \text{Carry } 1$$

• Next column ($4^3$):

$$\text{Carry } 1 \implies \text{Digit } 1$$

• Reading digits from left to right yields: $(1301)_4$.
• Decimal Verification:
• $m = 3(16) + 1(4) + 3(1) = 48 + 4 + 3 = 55_{10}$
• $n = 3(16) + 2(4) + 2(1) = 48 + 8 + 2 = 58_{10}$
• $m + n = 55 + 58 = 113_{10}$
• $(1301)_4 = 1(64) + 3(16) + 0(4) + 1(1) = 64 + 48 + 1 = 113_{10}$.
• Conclusion: The base 4 expansion is (1301)₄ (Option 3).

Correct option: (3) (1301)

• Computer I/O Organizations:
• Isolated I/O $\to$ (II): Uses separate address spaces and distinct machine instructions (e.g., IN, OUT) for I/O vs. memory access.
• Memory-mapped I/O $\to$ (I): Treats I/O ports as memory locations, sharing the exact same address space, control signals, and instructions (LOAD, STORE).
• I/O Interface $\to$ (IV): Hardware module that resolves electromechanical and data rate differences between the CPU/memory and peripheral devices.
• Asynchronous Data Transfer $\to$ (III): Requires explicit handshake/strobe control signals transmitted between communicating units that operate on independent clocks.
• Matching Result: (A)-(II), (B)-(I), (C)-(IV), (D)-(III) (Option 3).

Correct option: (3) (A)-(I), (B)-(1), (C)-(IV), (D)-(I)

• Asynchronous (Ripple) Counter:
• In the depicted digital logic circuit, JK flip-flops have their J and K inputs tied high (logic 1, toggle mode).
• Crucially, the external clock signal drives only the first flip-flop; each subsequent flip-flop is clocked by the output ($Q$ or $\bar{Q}$) of the preceding flip-flop.
• Because clock pulses ripple sequentially through the chain of flip-flops rather than triggering simultaneously, this circuit is a Ripple Counter (Asynchronous Binary Counter).
• Conclusion: Ripple Counter (Option 2).

Correct option: (2) Ripple Counter

• Lexical Analysis State Representations:
• In compiler design, during transition diagram simulation within a lexical analyzer:
• $S_0$: Represents the initial start state.
• $S_\emptyset$ / $S_w$: Represents the Empty state (dead state or non-accepting trap state where no valid token transition exists).
• Conclusion: Represents Empty state (Option 1).

Correct option: (1) Empty state